1. Field of the Invention
The present invention generally relates to a display, and more particularly, to a flat panel display having a dual gate panel.
2. Description of Related Art
In most applications, a flat panel display apparatus, such as, a thin film transistor-liquid crystal display (TFT-LCD), has served as a replacement of the conventional cathode ray tube (CRT) display apparatus. As compared with the conventional CRT display, the TFT-LCD apparatus has advantages, such as having relatively low voltage action, low power consumption, thin and small size, and light weight. To pursue better display quality, a flat panel display having a higher resolution suggests that the number of channels for the source driver and the number of data lines for the display panel would gradually increase. In order to reduce the number of channels of a source driver and the number of data lines of a display panel, a dual gate panel is developed.
FIG. 1 is a schematic diagram of a conventional dual gate panel 100. Referring to FIG. 1, on each pixel row, two neighboring sub-pixels share one data line. For example, on the pixel row SL1, the sub-pixel Pa and the sub-pixel Pb share the data line S1, and the sub-pixel Pc and the sub-pixel Pd share the data line S2. On the pixel row SL2, the sub-pixel Pe and the sub-pixel Pf share the data line S1, and the sub-pixel Pg and the sub-pixel Ph share the data line S2. Accordingly, with the application of a dual gate panel 100, the number of data lines and the number of channels of the source driver (not shown) may be reduced. Since two neighboring sub-pixels share one data line, each pixel row is disposed with two gate lines. As shown in FIG. 1, on the pixel row SL1, the sub-pixel Pa and the sub-pixel Pc are controlled by the gate line G1, while the sub-pixel Pb and the sub-pixel Pd are controlled by the gate line G2. On the pixel row SL2, the sub-pixel Pe and the sub-pixel Pg are controlled by the gate line G3, while the sub-pixel Pf and the sub-pixel Ph are controlled by the gate line G4. Similar arrangements are provided for other remaining sub-pixels.
The gate driver 120 and the source driver 130 in FIG. 1 are both controlled by the timing controller 110. Since the two neighboring sub-pixels commonly share one data line, in order to meet the specification requirement of the display, for example, maintaining the frame speed at 30 frames per second. Hence, the writing speed of the image data by the source driver 130 must increase significantly. For example, during the first half of the first horizontal scan period, the conventional gate driver 120 drives the gate line G1 to turn on the sub-pixels Pa and Pc. Concurrently, the conventional source driver 130 writes the driving signals into the sub-pixels Pa and Pc through the data lines S1 and S2. Thereafter, the conventional gate driver 120 drives the gate line G2 during the second half of the first horizontal scan period to turn on the sub-pixels Pb and Pd. At the same time, the conventional source driver 130 writes the driving signals into the sub-pixels Pb and Pd through the data lines S1 and S2. After this, the conventional gate driver 120 drives the gate line G3 during the first half of the second horizontal scan period to turn on the sub-pixels Pe and Pg. At the same time, the conventional source driver 130 writes the driving signals into the sub-pixels Pe and Pg through the data lines S1 and S2. Then, the conventional gate driver 120 drives the gate line G4 to turn on the sub-pixels Pf and Ph during the second half of the second horizontal scan period, while the conventional source driver 130 concurrently writes the driving signals into the sub-pixels Pf and Ph through the data lines S1 and S2.
As discussed above, the application of a dual gate panel 100 reduces the number of data lines. However, the data charging time of the sub-pixels is also reduced by half FIG. 2 illustrates signal waveforms of the line latch signal TP1, the polarity signal POL, and the data line S1. In FIG. 2, HP represents a horizontal scan period, HP1 represents the first half of the horizontal scan period HP, and HP2 represents the second half of the horizontal scan period HP, wherein HP1 and HP2 have the same length of the period. Since the charging time is reduced by half, driving imbalance between the first half and the second half of a same horizontal scan period often occurs. For example, as the data line S1 switches from the negative polarity to the positive polarity, the driving signals having the positive polarity are written into the sub-pixels Pa and Pb. Since the charging time is reduced by half, the sub-pixel Pa with the driving signal previously written thereinto is unable to achieve the required gray level due to a larger charging swing. For the sub-pixel Pb with the driving signal subsequently written thereinto, since the data line Si has already changed to the positive polarity, the sub-pixel Pb written with the positive polarity driving signal is able to achieve the required gray level due to a smaller charging swing. Accordingly, after the switching of polarity, driving imbalance and the generation of the mura defects likely occur to the sub-pixels (such as Pa) that are first written with the driving signal than the sub-pixels (such as Pb) that are written with the driving signal later.